1. Field of the Invention
The present invention relates to a charge-pump device with increased current output, in particular for use in a memory device, to which the following description will make explicit reference without however this implying any loss in generality.
2. Discussion of the Related Art
As is known, memory devices comprise voltage-booster devices which use charge-pump circuits. These charge-pump circuits generate boosted voltages (i.e. of a value higher than the supply voltage), which are necessary for performing read and modify (erasure or programming) operations on the memory devices. The charge-pump circuits must moreover supply at their output the levels of current necessary for performing the aforesaid read and modify operations.
It is moreover known that charge-pump circuits have significant problems of power consumption and of area occupation, above all when the memory devices in which they are incorporated are used in applications that require low levels of power consumption and small overall dimensions, such as, for example, portable applications (digital cameras, Mp3 readers, cellphones, smart cards, etc.).
Furthermore, the increase in parallelism and the reduction in the programming times in current memory devices make it necessary to supply an increasingly higher current by the charge-pump circuits. Said levels of current are difficult to obtain with existing charge-pump circuits without allocating a large area on silicon, as explained hereinafter with reference to FIGS. 1-4.
In particular, FIG. 1 shows a charge-pump circuit 1 of a known type, formed by a plurality of elementary stages 2 (only two of which are shown in FIG. 1). The elementary stages 2 are connected in a cascaded fashion between an input 3 and an output 4 of the charge-pump circuit 1. The input 3 is connected to a low-voltage supply line 5, set at a supply voltage VDD, for example of 1.6 V, whilst the output 4 supplies an output voltage Vout, generally higher than the supply voltage VDD, to a load 6. The load 6 is made up, for example, of the column capacitance CL of a memory array (not shown) of the memory device incorporating the charge-pump circuit 1, and of a resistor RL, connected in parallel to the column capacitance CL, and representing the power consumption due to memory internal operations.
Each elementary stage 2 receives at input two of four phase signals A, B, C and D provided by a phase-generator stage (not shown). In particular, the elementary stages 2 set in an odd position in the cascade (which are designated in FIG. 1 by the reference 2i and are referred to in what follows as “odd elementary stages” 2i) receive the phase signals A and B, whilst the elementary stages 2 set in an even position in the cascade (which are designated in FIG. 1 by the reference 2j and are referred to in what follows as “even elementary stages” 2j) receive the phase signals C and D. The phase signals A, B, C, D are logic signals that can assume a low value (equal to 0 V) or a high value (equal to VDD).
For convenience of description, only one of the elementary stages 2 is described, namely, an odd elementary stage 2i; the even elementary stage 2j has, in fact, identical components, which are designated by the same reference numbers followed by the identifier j.
In detail, each odd elementary stage 2i comprises: a pumping capacitor 10i; a charge-transfer transistor 11i; a boost capacitor 12i; a pre-charge transistor 13i; and a first buffer and a second buffer, represented schematically in FIG. 1 and referred in what follows as first inverter 15i and second inverter 16i, of a logic type.
The pumping capacitor 10i has a first terminal connected to a charge-transfer node 18i of the odd elementary stage 2i, and a second terminal connected to the output of the second inverter 16i, which in turn receives at its input the phase signal B. The charge-transfer transistor 11i has its drain terminal connected to the charge-transfer node 18i, its source terminal connected to a charge-transfer node 18j-1 of an even elementary stage 2j-1 that precedes the odd elementary stage 2i (or else to the input 3, if the odd elementary stage 2i is the first stage of the cascade), and its gate terminal connected to a pre-charge node 19i. The boost capacitor 12i has a first terminal connected to the pre-charge node 19i and a second terminal connected to the output of the first inverter 15i, which in turn receives at input the phase signal A. The pre-charge transistor 13i has its source terminal connected to the charge-transfer node 18j-1 of the preceding even elementary stage 2j-1, its drain terminal connected to the pre-charge node 19i, and its gate terminal connected to the charge-transfer node 18i. 
The even elementary stage 2j, as indicated, has the same circuit structure, and differs from the odd elementary stage 2i only in that the first inverter 15j receives at input the phase signal C, and the second inverter 16j receives at input the phase signal D.
Operation of the charge-pump circuit 1 is now described with reference to FIG. 2 as regards the first two stages of the cascade, the first odd elementary stage 2i and the first even elementary stage 2j. In particular, FIG. 2 shows: a clock signal CK; the phase signals A, B, C, D generated by the phase-generator stage; the voltage, designated by V1 (see also FIG. 1), at the charge-transfer node 18i; the voltage, designated by VG (see also FIG. 1), at the pre-charge node 19j (coinciding with the voltage on the gate terminal of the charge-transfer transistor 11j); and the voltage, designated by V2, at the charge-transfer node 18j (see also FIG. 1). A steady-state operating condition is further assumed; namely, it is assumed that the transients are complete and that the pumping capacitors 10i, 10j charge and discharge at each cycle of the clock signal CK by an amount of charge ΔQ proportional to the increase/decrease in the voltage across their terminals, designated by Vx.
At instant t0, the phase signals A and D have a low value, and the phase signals B and C have a high value. Consequently, the charge-transfer transistor 11i is on and the voltage V1 is equal to VDD; and the charge-transfer transistor 11j is off and the voltage V2 is equal to 3VDD−2Vx. In addition, the pre-charge transistor 13j is on and the voltage VG is equal to VDD.
At instant t1 (ideally corresponding to the rising edge of the clock signal CK), the phase signal A switches to the high value, turning off the charge-transfer transistor 11i. Then, after a first time interval Tdisov, which is necessary for preventing return of charge towards the supply line 5, at instant t2, the phase signal B switches to the low value, boosting the voltage V1 to a value equal to 2VDD. At the same instant, the voltage VG starts increasing, in so far as the pre-charge transistor 13j is still on, and the boost capacitor 12j charges to the new value assumed by the voltage V1.
At instant t3, after a second time interval Tdelay, necessary for increasing the voltage VG by a value ΔVG (for example, equal to 0.5 V), the phase signal D switches to the high value, and the voltage V2 decreases to the value 2VDD−2Vx. Consequently, the pre-charge transistor 13j turns off, and the voltage VG stops increasing.
After a time interval (equal to the first time interval Tdisov, given the symmetry of generation by the phase generator of the phase signals A and C starting respectively from the phase signals B and D), at instant t4 the phase signal C switches to the low value, the signal VG rises to the value 2VDD+ΔVG, thus switching the charge-transfer transistor 11j on.
From instant t4 a charge-transfer interval Tq begins, in which the amount of charge ΔQ is transferred from the pumping capacitor 10i of the odd elementary stage 2i to the pumping capacitor 10j of the even elementary stage 2j, in such a way as to raise the voltage V2 by the value Vx. At the end of the charge-transfer interval Tq, at instant t5 (ideally corresponding to the falling edge of the clock signal CK), the voltage V1 has fallen to the value 2VDD−Vx, and the voltage V2 has risen accordingly to the value 2VDD−Vx. Furthermore, at instant t5, the phase signal C switches again to the high value, and the voltage VG decreases to the value VDD+ΔVG turning off the charge-transfer transistor 11j and consequently interrupting charge transfer.
Once the first time interval Tdisov has elapsed again, starting from the switching of the phase signal C, at instant t6, the phase signal D switches to the low value, boosting the voltage V2 to the value 3VDD−Vx. Next, at instant t7, once the second time interval Tdelay has elapsed again, the phase signal B switches to the high state, and the voltage V1 decreases to the value VDD−Vx. After a time interval (equal to the first time interval Tdisov on account of the aforementioned symmetry of generation of the phase signals), at instant t8, the phase signal A switches to the low state, turning on the charge-transfer transistor 11i and giving rise to a new charge transfer from the supply line 5 to the pumping capacitor 10i. 
If the charge-pump circuit 1 comprises more elementary stages 2, the described steps of charge transfer occur in a synchronous way in all the odd elementary stages 2i in a first half-period of the clock signal CK, and subsequently in all the even elementary stages 2j in the second half-period of the clock signal CK. In this way, a gradual charge transfer from the input 3 to the output 4 of the charge-pump circuit 1 is obtained.
In particular, the current Iout (FIG. 1) supplied to the load 6 by the charge-pump circuit 1 is given by:Iout=fck·Cs·[(n+1)·VDD−Vout]
where n is the number of cascaded stages, fck is the frequency of the clock signal CK, and Cs is the capacitance of the pumping capacitor 10i, 10j. 
The charge-pump circuit 1 suffers from a major limitation as regards the maximum current Iout that can be supplied to the load.
In fact, as highlighted by the above formula, given the same voltages VDD and Vout and number of stages n, in order to increase the current Iout it is necessary to increase the capacitance Cs or else the frequency fck. However, increasing each of the aforesaid quantities entails specific disadvantages inherent in the requirements of power consumption and of area occupation.
In detail, an increase in the capacitance Cs entails a corresponding increase in the area occupied by the charge-pump circuit 1, an increase which, as indicated above, is inadmissible in many applications. For example, in order to reach the desired value of current Iout of approximately 7 mA, the charge-pump circuit 1 would have to occupy an area approximately four times greater as compared to the case where the current Iout itself were to have a value of 1.7 mA. Said increase further entails an increase in the production costs of the charge-pump circuit 1.
Furthermore, as highlighted in FIG. 3, the current Iout increases as the frequency fck increases, until the frequency fck reaches a value designated by fmax (depending upon the architecture of the individual elementary stage); instead, for values of frequency fck higher than fmax, the current Iout supplied decreases (so that the current Iout has a maximum designated by Ioutmax). Consequently, with the circuit described above, the increase in the frequency fck does not enable the desired increase in the current Iout to be obtained.
In fact, only a portion of each half-period of the clock signal CK is effectively dedicated to the charge transfer from one elementary stage 2 to the next. There exists a time interval, referred to in what follows as dead time Tm, which elapses between switching of the clock signal CK and switching of the phase signal C to the low value, at which the charge-transfer interval Tq starts. The duration of said dead time Tm is given by:Tm=Tdelay+2·Tdisov
and the charge-transfer interval Tq can thus be expressed as:
      T    q    =                    T        ck            2        -          T      m      
where Tck is the period of the clock signal CK.
As the frequency fck increases, and so as the period Tck decreases, the dead time Tm being constant, the charge-transfer interval Tq progressively decreases. Consequently, when a maximum value of the frequency fck (coinciding with the maximum frequency fmax of FIG. 3) is exceeded, the amount of charge ΔQ is no longer transferred in a complete way, and the boost capacitor 10i, 10j is no longer sufficiently charged. Deriving from this is a reduction in the current Iout for frequencies fck higher than the maximum frequency fmax.
FIG. 4 illustrates what has just been described, on the hypothesis that the current circulating in the charge-transfer transistor 11i, 11j, designated by It, has an exponential evolution during the charge-transfer interval Tq. In particular, the amount of charge not transferred at each half-period of the clock signal CK (hatched portion of the area under the curve of the current It) increases as the frequency fck increases.
Consequently, the need is felt to provide a charge-pump circuit which will enable an increase in the current supplied to the load, and at the same time will present a reduced area occupation.